1. Field of the Invention
The present invention relates to a switching system and, more particularly, to a control system installed in a D channel data link access protocol (LAPD) signal processor for supervising buffers which are adapted to individually temporarily store data signals therein. The LAPD signal processor with which the present invention is concerned is defined by International Telegraph and Telephone Consultative Committee (CCITT) Recommendations pertaining to the Integrated Services Digital Network (ISDN) user-network interface.
2. Description of the Prior Art
For the supervision of buffers provided in an ISDN switching system, some different approaches are available such as one which assigns a different receive queue to each data transmitted by a packet switching service and data transmitted by a circuit switching service, and one which does not discriminate between those two different kinds of data and, instead, monitors at layer 3 the lengths of queues that are awaiting transmission on individual D channels, on a channel-by-channel basis. The first-mentioned approach, or individual queue system, is disclosed in, for example, Takamura et al. "Study of Buffer Control System for ISDN Switching System," The Institute of Electronics and Communication Engineers of Japan, Technical Report SE86-56, pp. 43-48, 1986.
The principle of the individual queue system mentioned above is shown in FIG. 4 of the accompanying drawings. As shown, when a layer 3 processing section (CP.sup.3) takes in received signals, a different receive queue is assigned to each of packet switching service and circuit-switching service for each of a plurality of layer 2 processing sections (CPi.sup.2). In FIG. 4 and others, let arc representative of circuit-switched data signals and dots be representative of packet-switched data signals. As regards the assignment of buffers, priority is controlled by admitting a limited number of data signals from each of those queues at a period of t, for each of the circuit switching service and packet switching service. In receive processing, for example, the maximum number of signals which are derived from circuit switching service and can be admitted within the period t is selected to be greater than or at least equal to that of signals which are derived from packet switching service. Stated another way, circuit switching service data have priority over packet switching service data with respect to the assignment of buffers.
FIG. 5 illustrates the principle of the second-mentioned prior art control system in which the lengths of waiting queues are monitored at layer 3 for each D channel without discriminating between circuit switching and packet switched service data. As shown, the principle is such that circuit switching service data and packet switched service data are bracketed together and, once the waiting queue on any of the D channels exceeds a predetermined length, additional packet switching service on that channel is inhibited from being set up. Specifically, the system limits the total number of signals which can be admitted, instead of discriminating between circuit switching service data and packet switching service data with respect to the frequency of transmission on one D channel. To prevent buffers at any particular terminal equipment from being reserved for a long period of time, the system defines two different threshold values: a basic queue length N1 adapted for restriction, and a cancel queue length N0 which is shorter than the basic queue length N1 and adapted to cancel the restriction. The flow of packets toward the D channel is restricted when the actual queue length on the D channel becomes longer than the threshold value N1, and the restriction is cancelled when it becomes shorter than the other threshold value N0. As soon as the period of time during which the queue length on any D channel remains greater than the threshold value N1 exceeds a predetermined one, that channel is made busy.
Meanwhile, the assignee's copending Japanese patent application No. 72812/1985 proposes a system for eliminating the increase in the delay time of data which is ascribable to, for example, high calling rates of circuit switching service or packet switching service data due to the shortage of idle buffers which may be assigned to a receiving section. Specifically, the proposed system controls the number of buffers to be assigned to transmission and/or reception, depending upon the number of idle buffers which are available in a common buffer pool. As the number of idle buffers becomes smaller than a predetermined value, the number of buffers to be assigned to transmission and/or reception is cut down.
Another approach for the supervision of buffers in packet switching is disclosed in "Primary Study of DDX-2 Packet Switching System," Nippon Telegraph & Telephone Public Corporation, Study and Practical Use Report Vol. 26, No. 8, pp. 2383-2397. A packet switching system in accordance with this approach includes some buffers which are provided in a common buffer pool, and exclusive idle buffers for reception which are provided in a receive buffer pool and assigned to individual service access points.
In detail, when a receiving section receives data signals which are transmitted from various service access points such as packet switching service terminal equipment and other stations, or offices, it requests buffers for storing individual data. In response to this request, idle buffers in the receive buffer pool are assigned while, at the same time, an idle buffer request is applied to the common buffer pool to secure idle buffers. As the idle buffers are assigned, the receiving section stores the data signals originated by the individual service access points in their associated idle buffers. Upon completion of the reception, the information are sequentially lodged in their associated queues in the form of process waiting buffers, waiting for processing.
A processor takes in the waiting buffers from the queues, then analyzes destinations and other parameters of the data signals, and then sequentially stores them in their associated transmit queues in the form of transmit waiting buffers which individually correspond to the service access points for the destinations. If more than a predetermined number of transmit waiting buffers are present, the excess buffers are discarded as waste buffers. The discarded buffer areas are pooled in the common buffer pool.
A transmitting section sequentially takes out the transmit waiting buffers from the individual transmit queues and transmits the data signals stored in the respective buffer areas to terminal equipment, stations or offices, and other service access points for which the data signals are meant. The transmit acknowledging waiting buffers which are now idle wait for answers from their associated service access points. Upon arrival of an answer, each of the transmit acknowledging waiting buffers is returned to the common buffer pool to be reserved therein as an idle buffer.
Other buffer supervising systems for packet switching are described in "Area Congestion Control in Traffic Control System," National Convention of the Institute of Electronics & Communication Engineers of Japan, Communications Section, Vol-178, 1982, and "Traffic Control Algorithm for Packet Switching Network," Nippon Telegraph and Telephone Corporation, Study & Practical Use Report Vol. 35, No. 5, pp 53-61.
The system elaborated for congestion control as stated above performs restriction at a plurality of different levels based on the correlation between standard values of the ratio of a duration for which all the incoming trunk circuits are busy and those of the ratio of a duration for which all the hopper transaction memories, or buffers, are busy. The restriction is effected and cancelled by using the same threshold values.
On the other hand, the second-mentioned system applies congestion control having a plurality of levels to packet switching service data on the basis of correlation between the occupation rate of a processor and that of buffers.